The present invention relates generally to logic gates and more specifically to an improved current compensated logic gate.
Logic gates of the prior art are generally one of a series of logic gates receiving a plurality of logic signals from a previous logic gate which also has a plurality of inputs. Logic gates, for example, NOR and NAND, use a plurality of parallel connected input devices connected between a first supply voltage and an output and a pull-up or pull-down device respectively connected between the output and a second supply voltage. In a NOR/NOR or a NAND/NAND structure, activation of one of the input devices in the first stage will not produce a pure logic signal which represents an off signal to the second stage because of the voltage divider action between the on input device and the pull-up or pull-down device. Thus, the input device in the second stage is not completely off and thus developes a leakage current. This reduces the output logic voltage swing between logic high and logic low of the second stage.
The NOR gate and NAND gate may also be formed using a plurality of serial connected input devices connected between a first supply voltage and an output and a pull-down or a pull-up device, respectively, connected between the output and a second supply voltage. As in the parallel connected NOR or NAND gate, activation of one of the serial connected input devices and not total activation of a second serial connected device or not total deactivation of all the serial input devices forms the same voltage divider with the pull-up or pull-down device to create a leakage current which effects the subsequent stage or provides an undesirable output at the final stage. This problem is associated with any complex inverting logic which includes either parallel or serial connected input devices as well as combinations thereof which can produce a leakage current if they are not fully off.
With field effect transistors which operate in the enhancement mode, leakage current will also exist at high temperatures when the threshold goes through zero and they become operable in the depletion mode.
In order to maintain as large as possible voltage swing between the logic high and logic low signals, current compensation must be provided at the output of the second logic stage.
An object of the present invention is to provide a unique current compensation scheme for the output of a NOR or NAND gate.
Another object of the present invention is to provide a current compensation scheme for a logic array of NAND or NOR gates using the minimum number of devices.
Still another object of the present invention is to provide a current compensation scheme for a NAND or NOR gate which tracks the temperature and process variations of the logic gate.
An even further object of the present invention is to provide a current compensation circuit which accomodates leakage current resulting from high temperature depletion mode operation of field effect transistor elements.
A still even further object of the present invention is to provide current compensation for a complementary inverting logic gate.
These and other objects of the invention are attained by providing a current compensation generator having the same current capacity as the input devices of the inverting logic gate and a drive signal equivalent to the less than fully off drive signal provided by an input from a previous logic stage to generate the appropriate compensation current. The current compensation device includes a current mirror wherein the input devices of the inverting logic gate are in the controlled leg and a plurality of control devices equivalent in current capacity to those of the logic input devices are provided in the controlling leg. A voltage reference generator, having the same structure as a first logic gate stage with one input on, drives the control load devices in the controlling leg. To provide compensation for the high temperature range wherein the field effect transistors which make up the logic gate go into the depletion mode, the reference voltage would be the fully off logic signal which is generally one of the voltage source signals. Thus, the compensation circuit becomes active only in the depletion mode as does the logic gate. The first and second logic gate may be NOR/NOR or NAND/NAND.
For a logic array having a plurality of second stage logic gates, a plurality of controlled legs are connected in parallel to a single controlling leg having a single reference generator. The control devices and the input devices of the second input stage may be of identical current capacity and of the same number. Alternatively, the control load devices and the input devices of the logic gate may have the same current capacity and the ratio of the current capacity of the drive device in the controlling leg to the drive device in each of the controlled legs is equal to the ratio of the number of control load devices to the number of input devices of the respective logic gates. This allows a single controlling leg to control a plurality of logic gates having different total current capacities and consequently different current compensation requirements.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.